Methods for forming multi-layer vertical nor-type memory string arrays

ABSTRACT

A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a divisional application of U.S. patent application (“Parent Application”), Ser. No. 16/707,920, entitled “Methods for Forming Multi-layer Vertical NOR-type Memory String Arrays,” filed on Dec. 9, 2019, which claims priority of U.S. provisional application (“Provisional Application”), Ser. No. 62/777,000, entitled “Methods for Forming Multi-layer Vertical NOR-type Memory String Arrays,” filed Dec. 7, 2018.

The present application relates to U.S. patent application (“Non-Provisional Application I”), Ser. No. 16/107,732, “entitled “Three-dimensional vertical NOR Flash Thin film Transistor Strings,” Aug. 21, 2018, which is a continuation application of U.S. patent application Ser. No. 15/837,734, entitled “Three-dimensional vertical NOR Flash Thin film Transistor Strings,” filed on Dec. 11, 2017, which is a divisional application of U.S. patent application Ser. No. 15/343,332, entitled “Three-dimensional vertical NOR Flash Thin film Transistor Strings,” filed on Nov. 4, 2016, which is related to and claims priority of (i) U.S. provisional patent application Ser. No. 62/260,137, entitled “Three-dimensional Vertical NOR Flash Thin-film Transistor Strings,” filed on Nov. 25, 2015.

The present application is also related to U.S. provisional patent application (“Provisional Application II”), Ser. No. 62/625,818, entitled “Three-dimensional Vertical NOR Flash Thin-film Transistor Strings,” filed on Feb. 2, 2018; (ii) U.S. patent application (“Provisional Application III”), Ser. No. 62/630,214, entitled “Three-dimensional Vertical NOR Flash Thin-film Transistor Strings,” filed on Feb. 13, 2018; and (iii) U.S. provisional patent application (“Provisional Application IV”), Ser. No. 62/771,922, entitled “Staircase Structures for Electrically Connecting Multiple Horizontal Conductive Layers of a 3-Dimensional Memory Device,” filed on Nov. 27, 2018.

The disclosures of the Parent Application, the Non-Provisional Application and Provisional Applications I, II, III and IV are hereby incorporated by reference in their entireties.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention is related to 3-dimensional memory structures. In particular, the present invention is related to 3-dimensional memory structures organized in arrays of vertical NOR-type memory strings.

2. Discussion of the Related Art

Methods for forming multi-layer Vertical NOR-type memory string arrays have been described previously; for example, various variations of forming such memory arrays are disclosed in Non-Provisional Application and Provisional Applications II and III incorporated by reference above.

SUMMARY

According to one embodiment of the present invention, a method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local vertical bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stacks of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks. The present invention also addresses alignment issues incidental to etching the word line strips in two steps.

The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows memory structure 10 provided on and isolated from a conductive layer (“global interconnect lines”) 5, which includes numerous conductors, each extending along a first direction (X-direction).

FIG. 2 shows sacrificial dielectric layer 60 filling trenches 55, with excess dielectric material deposited on the top of memory structure 10 removed.

FIG. 3 shows another masking layer deposited on memory structure 10 and patterned to form masking structures 70.

FIG. 4 shows second set of trenches 80 fromed by etching through the multi-layers of memory structure 100, forming multi-layer stacks 90.

FIG. 5 shows memory structure 10 with cavities 35 after removal of SiN layer 30 in each mult-layer by a selective etch.

FIG. 6 shows metal layer 100 filling cavities 35 of the word line strips of memory structure 10.

FIG. 7 shows sacrificial dielectric layer 110 in trenches 80, after excess sacrificial dielectric material is removed from the top surfaces of memory structure 10 by any suitable planarization technique, such as CMP.

FIG. 8 shows patterning and etching of vias 120 in trenches 55 and 80 through memory structure 10.

FIG. 9 shows deposition of the following layers conformally in vias 120 of FIG. 8 :

vias 120: (i) tunneling dielectric layer 130, (ii) charge storage layer 140, (iii) blocking dielectric layer 150, (iv) channel layer 160, (v) liner layer 170, and (vi) sacrificial dielectric layer 180.

FIG. 10 shows the resulting memory structure 10 after the steps of creating vias of FIG. 8 and the deposition of various layers of FIG. 9 are repeated.

FIG. 11 shows shafts 200 defined in sacrificial dielectric layer 180 using photolithography and etched.

FIG. 12 shows each of shafts 200 being filled with semiconductor material 210, which form a common source region for the thin-film transistors to be formed along that via.

FIG. 13 shows drain semiconductor layers 220 being provided by repeating the steps of defining vias, etching liner layer 170 and filling vias with a semiconductor layer of FIGS. 11-12 .

FIG. 14 shows a second set of global interconnect lines 230 provided above memory structure 10 for contacting drain semicoductor layers 220.

FIG. 15 shows a staircase structure to enable contacting local word lines 240 of memory structure 10.

FIG. 16 shows vias and conductors 250 in the staircase structure of FIG. 15 to enable contacting of local word lines 240.

FIGS. 17A and 17B illustrate the phenomenon of ribboning, which is a stress-induced deformation of a microscopic rectangular feature.

FIGS. 18-21 , in conjunction with FIGS. 4-16 above, illustrate fabrication of memory structure 10, according to a second embodiment of the present invention.

FIGS. 22-29 , in conjunction with FIGS. 8-16 above, illustrate fabrication of memory structure 10, according to a second embodiment of the present invention.

To facilitate both cross-referencing among the figures and simplification of the detailed description, like elements in the figures are assigned like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In this detailed description, process steps described for one embodiment may be used in a different embodiment, even if the process steps are not expressly described in the different embodiment. When reference is made herein to a method including two or more defined steps, the defined steps can be carried out in any order or simultaneously, except where the context dictates or specific instruction otherwise are provided herein. Further, unless the context dictates or express instructions otherwise are provided, the method can also include one or more other steps carried out before any of the defined steps, between two of the defined steps, or after all the defined steps.

FIG. 1 shows memory structure 10 provided on and isolated from a conductive layer (“global interconnect lines”) 5 on planar surface 15 of a semiconductor substrate. The normal to planar surface 15 is along a first direction (Z-direction). The conductors in global interconnect lines 5 include numerous conductors, each extending along a second direction (X-direction) orthogonal to the Z-direction. The conductors in conductive layer 5 are each separated and insulated from its neighboring conductors along a third direction (Y-direction, substantially orthogonal to both the X-direction and the Z-direction). Global interconnect lines 5 provide electrical connectivity between vertical local word lines yet to be formed, and control, decode, voltage sources and sense circuits formed in the semiconductor substrate (not shown). Such connectivity can be either directly, or through select transistors (not shown).

Global interconnect lines 5 may include any suitable conductive material such as tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), chrome (Cr), molybdenum (Mo), cobalt (Co), or any combination of these materials. As shown in FIG. 1 , memory structure 10 includes 32 multi-layers (e.g., multi-layer 20), each of which may include, for example, silicon nitride (SiN) layer 30 and silicon oxide (SiO₂) layer 40. Alternatively, layer 30 may include, for example, a p-doped or n-doped silicon or silicon germanium, rather than silicon nitride. Each of the layers in each multi-layer may be deposited using any suitable technique, e.g., low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD, itself a form of CVD), sputtering, or evaporation, most preferably by PECVD. Although FIG. 1 shows 32 multi-layers, the number of multi-layers in memory structure 10 can be any suitable number (e.g., one, two, sixteen, sixty-four, or more). After depositing memory structure 10, a masking layer (e.g., a carbon-based masking layer) is deposited and patterned to form masking structures 50 using a photoresist layer (not shown) Masking structures 50 each have width L₂ and each separating from its neighboring masking structures by trenches of width L₁, with width L₂ preferably not less than twice desired width L₁. Width L₁ defines the desired width of the trenches between the active strips to be formed.

A first set of trenches 55 are then created by etching through the multi-layers of memory structure 10 using masking structures 50, followed by removal of masking structures 50. FIG. 2 shows sacrificial dielectric layer 60 filling trenches 55, with excess dielectric material deposited on the top of memory structure 10 removed. Removal of sacrificial dielectric layer 60 from the top of memory structure 10 may be accomplished using any suitable technique, such as chemical-mechanical polishing (CMP) or etchback, most preferably CMP. Sacrificial dielectric layer 60 may include any suitable material (e.g., SiO₂, porous SiO₂, boron doped SiO₂ (BSG), phosphorus doped SiO₂ (PSG), boron phosphorus doped SiO₂ (BPSG), SiOH, SiCOH, any combination of these materials, or any suitable material). Most preferably, sacrificial dielectric layer 60 is formed out of a material that can be etched much faster than SiN layer 30 and SiO₂ layer 40.

Thereafter, another masking layer is deposited on memory structure 10 and patterned to form masking structures 70, as shown in FIG. 3 . Masking structures 70, each of which extends over sacrificial dielectric layer 60 in one of trenches 50 and portions of the multilayers on both sides of that trench, are separated from each other by width L₁ (as in masking structures 50) to define second set of trenches 80 that are parallel to first set of trenches 55. FIG. 4 shows second set of trenches 80 fromed by etching through the multi-layers of memory structure 10, thus forming narrow multi-layer stacks (“word line stacks”) 90 each extending along the Y-direction. Each multi-layer in each word line stack forms a “word line strip.”. Word line stacks 90 each have width L₃ that is much less than width L₂ of masking structures 50 and 70. By using a relative large L₂ value in masking structures 50 and 70, a problem known as “ribboning” is avoided.

(FIGS. 17A and 17B illustrate the phenomenon of ribboning, which is a stress-induced deformation of a microscopic rectangular feature. FIG. 17A shows a microscopic rectangular feature (e.g., a feature formed out of developing a masking material) with intended dimensions width X1, length Y1 and height Z1. In some manufacturing processes, when the aspect ratio Z1/X1 exceeds 10, the stress in the rectangular feature may lead to deformation along length Y1, such that the resulting feature “ribbons” from an intended straight line to become a series of connected S-curves, such as shown in FIG. 17B. Ribboning is more acute with smaller widths, especially when width X1 is scaled below approximately 45 nm.)

In practice, due to limitations of existing lithography tools, some misalignment may occur, so that the overlaps of each masking structure 70 over the left and right stacks underneath it are not exactly equal. For example, if the target width L₃ is 50 nanometers and the worst-case misalignment is ±5 nanometers, then the left-side overlap may be as much as 55 nanometers wide, while the right-side overlap may be as narrow as 45 nanometer wide. This manufacturing variability in width causes into variability of the width of the yet to be formed even and odd metallic conductor word lines. In turn, the variability in width may cause higher electrical resistance of the narrower word lines. Such variability can be absorbed within the chip design, for example by treating the left and right side thin-film transistors of each stack as belonging to two separate groups, with each group being provided with its dedicated reference transistors or reference memory strings that are constituted from within their respective groups.

Next, as shown in FIG. 5 , SiN layer 30 of each word line strip in memory structure 10 are removed by a selective etch. SiN layer 30 may be removed using any suitable technique, such as a corrosive gas or a wet chemical acid or base. For example, SiN layer 30 may be removed by wet etching in phosphoric acid heated to 180° C. Etching stops when each SiN layer 30 is etched all the way to sacrificial dielectric layer 60 in trenches 55. As sacrificial dielectric layer 60 in trenches 55 are not materially etched, their support allows word line stacks 90 to maintain their intended structural forms (i.e., each narrow, long and tall along the entire length), even though the constituent SiN layer 30 in each word line strip is removed, thereby creating cavities or discontinuities 35 in word line stacks 90. Note that braces spanning between adjacent stacks 90 and placed at suitable intervals may not be needed to support the narrow active stacks under existing state-of-the-art technology. However, such braces may be required in the future for highly scaled 3-dimensional memory arrays when width L₃ becomes even narrower, or when the word line stacks are exceedingly tall (e.g., the number of word line strips is exceedingly large), so that it becomes prudent to support the very long word line stacks at suitable intervals.

One or more metal layers are then provided to form metal layer 100, which fills cavities 35 in each word line strip. Metal layer 100 is then removed from the sidewalls of trenches 80 by a suitable etch, leaving metal layer 100 only in the word line strips, as shown in FIG. 6 . In some embodiments, metal layer 100 is further recessed by selectively etching up to approximately 6 nanometers away from the sidewalls of trenches 80, so as to accommodate an oxide cap layer or silicon barrier cap layer to be placed therein, as is known by those of ordinary skill in the art. The oxide cap layer or silicon barrier cap layer separates metal layer 100 from directly contacting a charge trapping layer yet to be formed. Metal layer 100 may be any suitable material, such as TiN, TaN, Ta, W, Mo, or any combination of these metals, deposited by any suitable technique, such as ALD, CVD, PVD, sputtering, evaporation, or any suitable combination of these techniques, most preferably ALD for a liner metal like TiN and CVD for a filler material such as W or Mo. As shown in FIG. 7 , a combination of tungsten layer 105 between thiner TiN layer 107 form metal layer 100.

FIG. 7 shows sacrificial dielectric layer 110 deposited in trenches 80, after excess sacrificial dielectric material is removed from the top surfaces of memory structure 10 by any suitable planarization technique, such as CMP. Sacrificial dielectric layers 60 and 110 are then patterned using photolithography and etched to provide elongated vias 120 that extend through the height of memory structure 10 (i.e., along the Z-direction), exposing the sidewalls of word line stacks 90, as shown in FIG. 8 . Adjacent ones of vias 120 in each trench is separated by a predetermined distance, such as the length along the Y-direction of each via 120.

The following films are then successively deposited conformally in elongated vias 120: (i) tunneling dielectric layer 130, (ii) charge storage layer 140, (iii) blocking dielectric layer 150, (iv) channel layer 160, (v) and optional liner layer 170, and (vi) sacrificial dielectric layer 180. These layers may be deposited using any suitable technique, e.g., as LPCVD, CVD, ALD, PVD, or evaporation, most preferably LPCVD and ALD. Tunneling dielectric layer 130 may be any suitable material for which charge carriers may tunnel through (e.g., silicon dioxide). Tunneling dielectric layer 130 may be any suitable thickness (e.g., 0.5 to 10.0 nm). Charge storage layer 140 may be any suitable material, such as: (i) SiN or silicon rich SiN, in any suitable form (e.g., amorphous, nanocrystalline or polycrystalline), or (ii) germanium nanocrystals in a silicon nitride, silicon oxide matrix, silicon oxide, or silicon-rich silicon oxide. Charge storage layer 140 may be any suitable thickness (e.g., 0.5 to 20 nm). Blocking dielectric layer 150 may be silicon oxide, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide, or any suitable combination of these materials. Blocking dielectric layer 150 may be any suitable thickness sufficient to block charge carriers from passing through (e.g., 3 to 30 nm).

Channel layer 160 is a suitable n-type or p-type semiconductor material (e.g., silicon, silicon germanium, or indium gallium zinc oxide (IGZO), or zinc oxide) with a suitable thickness (e.g., 2 to 30 nm) and typically in-situ relatively lightly doped or undoped. Sacrificial dielectric layer 180 may include any suitable material, such as SiO₂, porous SiO₂, boron-doped SiO₂ (BSG), phosphorus-doped SiO₂ (PSG), boron-phosphorus-doped SiO₂ (BPSG), SiOH, SiCOH, or any combination of these materials. Optional liner layer 170 is a material suitable for serving as as etch-stop for a yet to be performed etch of sacrificial dielectric layer 180 (e.g., aluminum oxide or silicon nitride) with any suitable thickness (e.g., 0.5 to 5 nm). After deposition of these layers conformally into vias 120, excess material may be removed from the top of memory structure 10, followed by planarization using any suitable technique, such as CMP.

Thereafter, the steps of creating vias of FIG. 8 is repeated to create vias 125 by removing the remaining portions of sacrificial dielectric layers 60 and 110 of trenches 55 and 80, while protecting the deposited layers in vias 120. The same materials are then deposited conformally in vias 125 as in vias 120: (i) tunneling dielectric layer 130, (ii) charge storage layer 140, (iii) blocking dielectric layer 150, (iv) channel layer 160, (v) optional liner layer 170, and (vi) sacrificial dielectric layer 180. The resulting structure is shown in FIG. 10 . In FIG. 10 , the dielectric material in trenches 55 and 80 are now replaced by adjacent columns of successively deposited layers between word line stacks 90. The charge storage material in this second set of shafts may have different characteristics, if desired, than those of the charge storage material in the earlier set of shafts.

Shafts 200 are then defined in sacrificial dielectric layer 180 using photolithography and etched, as shown in FIG. 11 . Each of shafts 200 extends from the top of memory structure 10 down to global interconnect lines 5 through openings in the isolation layer between memory structure 10 and global interconnect lines 5. During etching of shafts 200, which may be a high-power dry etch of sacrificial dielectric layer 180, the sidewalls of channel layer 160 are protected by liner layer 170, which is resistant to the etch. As shown in FIG. 11 , adjacent shafts along the X-direction are aligned to each other, however alternatively they can be staggered relative to each other. Only every other adjacent shafts of shafts 200 along the X-drection are exposed to the same conductor in underlying global interconnect lines 5. The portion of liner layer 170 exposed in each of shafts 200 is then removed, for example, by a wet etch which does not damage underlying channel layer 160.

Each of shafts 200 is then filled with semiconductor material 210, which form a common source region for the thin-film transistors to be formed along that via. Source semiconductor layer 210 may be any suitable heavily n-doped or p-doped material, such as silicon, germanium, or silicon germanium. Alternatively the shafts are only partically filled along their walls with the deposited source material, the remaining space in the cavity is then filled with a low-resistivity material such as TiN or Tungsten (not shown). Any portion of semiconductor layer 210 covering the top of memory structure 10 may be removed using a planarisation technique. such as CMP. The resulting structure is shown in FIG. 13 . Source semiconductor layer 210 is electrically connected to the global interconnect lines 5.

Drain semiconductor layers 220 are provided by repeating the steps of defining and etching vias in sacrificial dielectric layer 180, etching liner layer 170 and filling vias with a heavily n-doped or p-doped semiconductor layer 210 of FIGS. 11-12 , except that etching of vias for drain semiconductor layer 220 does not punch-through to global interconnect lines 5, so that drain semiconductor layer 220 does not contact global interconnect lines 5. The resulting structure is shown in FIG. 13 . Source semiconductor layers 210 are marked by an “X” in FIG. 13 . A second set of global interconnect lines, labeled global interconnect lines 230 above memory structure 10 for contacting local drain semicoductor layers 220, as shown in FIG. 14 , forming global bit lines that connect every other adjacent shaft 220, either directly or through selection transistors, to circuitry in the substrate. At this point, source semiconductor region 210 and drain semiconductor layer 220 of each of shafts 200 form the common source region and the common drain regions (“bit lines”) of thin-film storage transistors of a vertical NOR-type (VNOR) memory string, each thin-film transistor being formed at the lateral overlapping region between a word line strip 100 and channel layer 160, tunnel dielectric layer 130, charge storage layer 140 and blocking dielectric layer 150. In one embodiment, each word line strip 100 controls NOR-type memory transistors on each of its side edges.

In a VNOR memory array according to the present invention, a typical nominal minimum width L₁ of a word line strip is 50 nanometers, while the nominal minimum width of trench 55 or 80 separating adjacent word line stacks may be 80 nanometers, and the height of a word line stack with 32 active layers may exceed 2,000 nanometers (2 microns). The aspect ratio of a stand-alone word line stack of 50 nanometer width would therefore be 2000/50, or 40:1, which would be severely challenging to remain standing erect during an etch, let alone through successive process steps, which would adversely impact yields and cost. However, using a method according to the present invention, the width L₂ of each masking structures 50 and 70 of FIGS. 1 and 3 is 50+80+50=180 nanometers, therefore the aspect ratio of an etch using masking structures 50 or 70 is 2,000/180, or 11:1.

In some embodiments, for die size considerations, it may be advantageous to place some circuitry (e.g., decoding circuits, and some read, write and erase supply voltage sources) that is electrically connected through global interconnect lines 5 or global interconnect lines 230 in a part of the semiconductor substrate that is directly underneath memory structure 10. (These decoding circuits and voltage sources are not shown in FIG. 14 .) Electrical connections between global interconnect lines 5 and these circuits in the semiconductor substrate are readily available. To electrically connect these circuits in the semiconductor substrate to global interconnect line 230 above memory structure 10 may require providing additional vertical connectors on one or more sides of memory structure 10 as well as conductors positioned between global interconnect lines 230 and the circuits in the semiconductor substrate. In one embodiment, such circuitous paths may be avoided by providing vertical conductors connecting global word lines 220 to the circuits in the semiconductor substrate directly through the densely packed memory structure 10 and the densely spaced global interconnect lines 5. These vertical conductors may be implemented by having selected ones of local vertical source semiconductor layer 210 or local vertical drain semiconductor layer 220 to also serve as conductors for connecting to the circuits in the semiconductor substrate. When used in that manner, one option is to fill the vias with a more conductive material (such as metal) instead of a heavily doped semiconductor. To establish electrical paths using these vertical conductors may require an extra mask and an etch step to punch-through via openings at the bottom of their respective shafts at locations directly above or close to where such circuits are placed in the semiconductor substrate.

In some embodiments, global interconnect lines 5 underneath memory structure 10 need not be formed when vertical local source semiconductor layer 210 and vertical local drain semiconductor layer 220 are all connected to global interconnect lines 230 formed above memory structure 10. Such an arrangement obviates the punch-through masking and etch steps required to connect source semiconductor layer 210 to global interconnect lines 5. Conversely, semiconductor layer 210 and drain semiconductor layer 220 may all be contacted through the punch-through vias to global interconnect lines 5 at the bottom of memory structure 10. In either case, one of the two sets of global interconnect lines may be obviated, provided that the global interconnect lines have approximately one-half the pitch of global interconnect lines 5 or global interconnect lines 230, which may require double exposures or more advanced lithography.

Connections to the local word lines are made by a “staircase” method. In a staircase structure, the word line strips in a word line stack are cut to successively greater lengths to allow vertical conductors to contact the local word lines of successive word line strips at the steps. A similar method to form staircase structures is disclosed, for example, in Provisional Application IV incorporated by reference above. After memory formation and connection to top and bottom global wordlines, connections to the wordlines are made by a “staircase” method. The staircase structure is made by first providing a masking layer to expose and etch away a portion of the top word line strip in each word line stack exposing metal layer 100 of the word line strip, and successively (i) recessing the masking layer; (ii) etching away a portion of each of the exposed word line strips, exposing a portion of metal layer 100 at each step, until each of word line strips in the word line stack—except the bottom word line strip—has a portion removed as shown in FIG. 15 . FIG. 15 shows only an end portion along the length of the word line strips) of memory structure 10. (The portion between the end portions, i.e., the portions containing the thin-film transistors, are the portions shown in FIGS. 1-14 .) Using a photoresist recess technique discussed, for example, in Provisional Application IV, a masking layer is recessed along the Y-direction from one or both ends without an additional photo-lithographical step to expose successive word line strips.

A dielectric material is then deposited over the staircase structure and planarized by CMP. FIG. 16 shows that the result dielectric material is patterned and etched for via openings, which are then and then filled with a conductive material (e.g., a refractory metal, such as tungsten) 250 to provide contacts to the ends of word line layer 240 in each active layer exposed by the staircase structure. In this manner, each word line is connected to selective circuitry (e.g., a decoder and a voltage source) in the semiconductor substrate, or on a separate companion integrated circuit. Such an integrated circuit may be connected to circuitry in the semiconductor substrate using a flip-wafer technique (e.g., through a multitude of miniature copper studs between connected wafers) known in the art.

According to another embodiment of the present invention, structural support for high aspect ratio word line strips is provided by dielectric pillars formed prior to word line strip formation. As shown in FIG. 18 , memory structure 10—including global interconnect lines are formed, in substantially the same manner as discussed above with respect to FIG. 1 . However, unlike mask layer 50 of FIG. 1 , mask layer 260 is provided, which is patterned to allow shafts 265 to be etched through the word line stacks. After etching of shafts 265 and removal of mask 260, shafts 265 are filled by s dielectric material to form dielectric pillars 270, with excess dielectric material suitably removed (e.g., by CMP or etch back) from the top of structure 10, as shown in FIG. 19 . Suitable dielectric materials for dielectric pillars 270 include any suitable material (e.g., SiO₂, SiN, SiON, SiC, SiCOH, PSG, BSG, or BPSG, most preferably SiO₂), deposited using any suitable technique (e.g., ALD, LPCVD, or PECVD, most preferably LPCVD).

Memory structure 10 is then patterned to form word lines stacks 285 by creating trenches 280 with mechanical support from dielectric pillars 270, which are not substantially etched. The resulting structure is shown in FIG. 20 . The dielectric pillars 270 provide mechanical support to the high aspect—ratio stacks 280 of word line strips. Sacrificial dielectric material material 290, which may be the same material as dielectric pillars 270, is deposited to fill trenches 280. Excess sacrificial dielectric material 290 may be removed from the top of word line stacks 285 using, for example, CMP or etchback. Thereafter, a masking layer (not shown) may be deposited and patterned, so as to allow sacrificial dielectric material 290 to be removed from every other ones of the filled trenches 280. Memory structure 10, after removal of the masking layer and sacrificial dielectric material 290 form every other ones of trenches 280, is shown in FIG. 22 . The rest of the fabrication of memory structure 10 may proceed according to the description above and FIGS. 4-16 .

Yet another embodiment of the present invention uses stacked masks to form the word line strips. Referring to FIG. 22 , first masking layer 300 is deposited and patterned. First masking layer 300 defines the final dimension and pitches of the word line stacks. After the first masking layer 300 is formed, second masking layers 310, shown in FIG. 23 , is deposited and patterned. Second masking layer 310 has a larger pitch and dimension than first masking layer 300, and is provided on top of first masking layer 300. Second masking layer 310 defines every other final word stacks in memory structure 10, as shown in FIG. 23 . FIG. 23 also shows trenches 320, which are etched through memory structure 10 after second masking layer 310 is defined.

A planarization step (e.g., an etch-back step) removes remove a portion of second masking layer 310, such that the top of second masking layer 310 is flush with first masking layer 300. Sacrificial dielectric material 330 is then deposited to fill trenches 320, followed by removal of excess sacrificial dielectric material 330 from the top surfaces of first masking layer 300 and second masking layer 310, such as shown in FIG. 24 .

The remainder of second masking layer 310 is then removed by a selective etching technique. First masking layer 300 and sacrificial dielectric layer 330 are then used as masks to etch a second set of trenches 340, as shown in FIG. 25 . Thereafter, the remainder of first masking layer 300 is then remove by a selective etching technique, as shown in FIG. 26 .

The silicon nitride layers (40) are then removed by a selective etching technique, leaving cavities 350, such as shown in FIG. 27 . Metal layers 360 are then deposited to fill trenches 340 and cavities 350. Metal deposited on the sidewalls of trenches 340 and top surfaces of sacrificial dielectric material 330 are then removed by an isotropic etching technique, leaving metal 360 filling cavities 350, as shown in FIG. 28 . The details of this metal replacement process have been detailed in description above in conjunction with FIGS. 4 and 5 . Thereafter, sacrificial dielectric material 370 is deposited into trenches 340, followed by removal of any excess sacrificial dielectric material 370 from the top surfaces of memory structure 10. The rest of the fabrication of memory structure 10 may proceed according to the description above and FIGS. 8-16 .

The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims. 

We claim:
 1. A method for high aspect ratio etching, comprising: preparing above a surface of a semiconductor substrate a plurality of multi-layers, stacked one on top of another along a first direction substantially orthogonal to the surface of the semiconductor substrate, wherein each multi-layer comprising a first layer and a second layer, wherein the first layer comprises a first dielectric material and the second layer comprises a first material; patterning and etching the multilayers along the first direction using a first mask to form a first set of trenches that divide the multi-layers into a first group of multi-layer stacks, wherein each of the first set of trenches extends along a second direction substantially parallel to the surface of the semiconductor substrate; filling the first set of trenches with a second dielectric material; patterning and etching the first group of multi-layer stacks along the first direction using a second mask to form a second set of trenches that create, out of the first group of multi-layer stacks, a second group of multi-layer stacks, wherein each of the second set of trenches extends along the second direction parallel the first set of trenches; filling the second set of trenches with the second dielectric material; and selectively etching a first portion of the second dielectric material in the first and second sets of trenches to provide a first plurality of shafts that extends along the first direction; depositing a semiconductor layer of a first conductivity conformally; and filling each shaft with a third dielectric material.
 2. The method of claim 1, wherein etching the multi-layer and etching the first group of multi-layer stacks each involve an etch of an aspect ratio less than
 40. 3. The method of claim 1, wherein the second mask comprises mask structures each overlapping at least two neighboring ones of the first group of multi-layer stacks and one of the first set of second dielectric material-filled trenches therebetween.
 4. The method of claim 1, wherein the first material comprises a conductive material.
 5. The method of claim 1, further comprising depositing a storage material conformally on the sidewalls of each shaft.
 6. The method of claim 1, wherein the semiconductor layer of a first conductivity comprises one or more of: indium gallium zinc oxide (IGZO) and zinc oxide.
 7. The method of claim 1, further comprising: selectively etching a first via and a second via through the third dielectric material in each shaft; and filling the first and second vias in each shaft with a semiconductor material of a second conductivity opposite the first conductivity or a conductive material.
 8. The method of claim 7, further comprising, prior to filling each shaft with the third dielectric material, depositing a liner layer over the semiconductor layer of the first conductivity, and wherein the method further comprises, prior to filling the first and second vias in each shaft by the semiconductor material of the second conductivity, removing the liner layer to expose the semiconductor layer of the first conductivity.
 9. The method of claim 7, further comprising, prior to preparing the multi-layers, providing a plurality of conductors above the surface of the semiconductor substrate, each conductor extending along a third direction substantially orthogonal to each of the first and second directions.
 10. The method of claim 9, wherein the conductors are isolated from the multi-layers by an isolation layer, wherein etching the first and second vias in each shaft further comprises etching through the isolation layer to provide a conductive path between the semiconductor material of the second conductivity or the conductive material in selected ones of first and second vias and to be electrically connected to corresponding ones of the conductors.
 11. The method of claim 7, further comprising providing a plurality of conductors above the second group of multi-layer stacks, each conductor extending along a third direction substantially orthogonal to each of the first and second directions.
 12. The method of claim 11, further comprising providing conductive paths to enable the semiconductor material of the second conductivity or the conductive material in selected ones of the first and second vias to be electrically connected to one of the conductors.
 13. The method of claim 11, further comprising: providing circuit elements in the semiconductor substrate; and electrically connecting the semiconductor material of the second conductivity or the conductive material in selected ones of the first and second vias to corresponding ones of the circuit elements, each of the circuit elements being situated substantially below its corresponding first and second vias.
 14. The method of claim 13, further comprising providing an isolation layer between the circuit elements and the multi-layers, wherein electrically connecting selected ones of the semiconductor material of the second conductivity or the conductive material in the selected ones of the first and second vias to their corresponding circuit elements comprises creating conductive paths through the isolation layer.
 15. The method of claim 7, the semiconductor material of the second conductivity or the conductive material partially fills the first and second vias, the method further comprising, thereafter, filling the first and second vias by a low resistivity conductor material.
 16. The method of claim 5, further comprising: selectively etching a second portion of the second dielectric material in the first and second sets of trenches to provide a second plurality of shafts that extends along the first direction; depositing a storage material conformally in each of the second plurality of shafts; depositing the semiconductor layer of the first conductivity conformally over the storage material in each of the second plurality of shafts; and filling each of the second plurality of shafts with the third dielectric material.
 17. The method of claim 16, wherein the storage material in the second plurality of shafts has different characteristics than those of the storage material in the first plurality of shafts.
 18. The method of claim 1, the first material comprises a sacrificial layer, the method further comprising selectively replacing the sacrificial layer by a conductive material.
 19. The method of claim 18, wherein replacing the sacrificial layer comprises selectively etching the sacrificial layer laterally through the second set of trenches up to the second dielectric material in the first set of trenches.
 20. The method of claim 1, further comprising creating a staircase structure at one or more ends of each multi-layer stack, wherein each staircase structure has steps that successively extends the layers of the multi-layer stack along the second direction and wherein each step exposes a conductive layer in a multi-layer in the multi-layer stack.
 21. The method of claim 20, further comprising providing an electrically insulating material over the staircase structure and providing via connections along the first direction to electrically connect to the conductive layer in each of the steps of the staircase structures. 